The present invention relates generally to voltage references and more specifically to punch-through diodes.
Many analog circuits have differential inputs wherein the inputs are the bases of two bipolar devices forming the differential pair. These inputs are subject to large differential voltages under some conditions. When the differential voltage at the input exceeds the blocking voltage between the base terminals (BV.sub.EBO +V.sub.BE, for a simple common emitter differential pair), the emitter-base junction of one member of the input pair breaks down. Such breakdown can damage the device, resulting in reduced HFE (especially at low current), degrade the V.sub.BE match and increase noise. A number of circuits of the prior art use diodes with breakdowns lower than BV.sub.EBO connected between the bases of the input transistors, to protect the input devices from this problem.
A typical prior art circuit is illustrated in FIG. 1 as including input transistors Q1 and Q2 receiving input voltages V1 and V2 at their bases and having their emitters connected in common with a current source CS. A pair of zener diodes Z1 and Z2 are connected in opposition across the inputs or bases of the differential input pair. The zener diodes generally have a breakdown voltage of 5 volts where the BV.sub.EBO of the bipolar transistors is generally above 6 volts. For appropriate voltage differential, one of the zener diodes breaks down creating a current path between the inputs V1 and V2 to protect the input devices Q1 and Q2.
One of the problems with the zener diode scheme of FIG. 1 is that the protection diode Z1, Z2 is forward biased during protection. This forward biasing develops a large stored charge of excess carriers. When the input returns to a normal range from the large differential voltage which broke down the protection zener diode Z1, Z2, a stored charge is still present and disrupts proper action of the differential pair until it has been removed or recombined. Thus while providing protection for the input pair Q1, Q2, diodes Z1, Z2 disrupt the normal operation of the circuit. Thus there is a need for a voltage protection device which does not store excess charge when it operates as a protecting device.
Thus it is an object of the present invention to provide a voltage referenced device which does not store charge when it acts as a protecting device.
Another object of the present device is to provide a punch-through diode structure which minimizes charge storage.
These and other objects of the invention are achieved by providing a punch-through diode as a voltage reference in a circuit as well as an improved punch-through diode. The punch-through diode uses majority carriers for conduction so that it minimizes charge storage. A punch-through diode includes a first and second gate forming first and second junctions respectively with a first region and the gates are spaced from each other by a first portion of the first region. The diode conducts current between the first and second gates when the voltage difference between the first and second gates depletes the first portion of the first region between the first and second gates. This is the punch-through majority carrier operation. A first gate may be a second region of a first conductivity type forming a PN junction with a first region of a second conductivity type or may be a gate material which forms a Schottky barrier junction with the first region. The second gate is a third region of the first conductivity type forming a PN junction with the first region.
The punch-through diode may have an FET structure wherein the first junction is the top gate-channel junction of the FET structure and the second junction is the bottom gate-channel junction of the FET structure. Alternatively, the diode may have a bipolar transistor structure wherein the first junction is the emitter-base junction of the bipolar structure and the second junction is the collector-base junction of the bipolar structure. In either case, it is the channel or the base which is depleted which causes flow between the top and bottom gate or the emitter and collector respectively. The first portion of the first region has a lower impurity concentration and a smaller thickness than the remainder of the first region. Wherein the first gate is a second region of a conductivity type opposite the conductivity type of the first region, it also has a first portion extending over the first portion of the first region and into the remainder of the first region. The first region of the first gate also has a second portion in the remainder of the first region of a greater thickness than the first portion of the second region.
When either of the gates has a low series resistance, and the other has a high series resistance the other gate may have two separate contacts for a Kelvin connection of the diode to reduce the effect of series on resistance performance. Wherein both of the gates have high series resistance, one or both may have two separate contacts for Kelvin connections of the diode. The Kelvin connection in combination with an operational amplifier provides a voltage references.
For the use of the punch-through diode in a differential amplifier, a first punch-through diode is connected between the first and second inputs for conducting current from the first input to the second input when the voltage at the first input exceeds the voltage at the second input beyond the normal operating voltage range of the amplifier. A second punch-through diode is connected between the first and second inputs for conducting current from the second input to the first input when the voltage at the second input exceeds the voltage at the first input beyond the normal operating voltage range of the amplifier. These diodes are connected in anti-parallel configuration as compared to the series configuration of FIG. 1 of the prior art.
The unique punch-through structure may be also used in a clamp or cascoded transistor circuit. A punch-through diode is in a circuit connected to the two current path terminals of a first transistor to be clamped for establishing an operating voltage across the first transistor which is substantially independent of the voltage on a control terminals of the first transistor relative to the supply voltage of the circuit. The punch-through diode has the same structure as the first transistor. Wherein the first transistor is an FET, the punch-through diode would have an FET structure wherein the first and second terminals of the diode would represent the top and bottom gates of the first field effect transistor forming junctions with and separated by the channel which is the punch-through region. Wherein the first transistor is a bipolar transistor, the punch-through diode would have the structure of the bipolar transistor with its first and second terminal represented by the collector and emitter and forming junctions respectively with and separated by the base which is the punch-through region.
In a cascode configuration, a second transistor has its current path connected in a series with the current path of the first transistor and a third transistor is connected in a series with the punch-through diode. A control terminal of the third transistor is connected to the first transistor's current path and the control terminal of second transistor is connected to the second terminal of the punch-through diode. The second and third transistors are of opposite conductivity types.
The top gate, bottom gate and channel structure as well as the collector, base and emitter structure are those produced in the standard process of creating field effect transistors and bipolar transistors. Thus the punch-through diodes having FET and bipolar structures may be produced simultaneously with the FET and bipolars in an integrated circuit. This allows maximum tracking for FETS as well as reduction of the process steps to produce the additional structure for both FETS and bipolars.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.